1. Field of the Invention
The present invention relates a semiconductor device, and more particularly, to a method for forming a wiring in a semiconductor device, which allows to form a micron pattern below a critical resolution of an exposure.
2. Background of the Related Art
Even though a line width decreases the more as a device packing density of semiconductor devices becomes the higher, there has been a limitation in formation of a micron pattern only by an exposure due to the critical resolution in the photolithography.
A related art method for forming a wiring in a semiconductor device will be explained with reference to the attached drawings. FIG. 1 illustrates a plan view of a related art wiring in a semiconductor device, FIGS. 2a and 2b illustrate sections showing structures across lines I-I' and II-II' in FIG. 1 without a cap layer respectively, and FIGS. 3a and 3b illustrate sections showing structures across lines I-I' and II-II' in FIG. 1 with a cap layer, respectively.
Referring to FIG. 1, the semiconductor device is provided with a cell array region, and a pad and peri region. As can be known from FIG. 1, though the pad and peri region has a comparatively large line width, the cell array region has a relatively small line width.
The related art method for forming a wiring in a semiconductor device will be explained.
Referring to FIGS. 2a and 2b, a conduction layer 2 and a photoresist film 3 are deposited on a substrate 1 in succession for use as a wiring layer. And, the photoresist film 3 is subjected to patterning by exposure and development to form a wiring pattern mask. The wiring pattern mask is used in removing the conduction layer, selectively. Then, the photoresist film 3 is removed to form wiring in the cell array region and the pad and peri region, respectively.
Referring to in FIGS. 3a and 3b, if a cap layer is provided on the wiring layer, the conduction layer 2 for use as the wiring layer, a cap layer 4 and the photoresist film 3 are deposited on the substrate 1 in succession. And, the photoresist film 3 is subjected to patterning by exposure and development, to form a wiring pattern mask. The wiring pattern mask is used in removing the cap layer 4 and the conduction layer 2 selectively. Then, the photoresist film 3 is removed, to form wiring on the cell array region and the pad and peri region, respectively.
And, though not shown, sidewalls may be used for forming a micron pattern. However, this method forms unnecessary pattern because the sidewalls are formed in four sides.
Thus, the related art method for forming a wiring in a semiconductor device has the following problems.
First, if the wiring is formed by exposure, a micron pattern below the critical resolution of the exposure can not be formed.
Second, even if a micron pattern beyond the micron pattern formation limit of the present exposure is formed by applying the sidewall method, the formation of the sidewalls all around a sacrificial pattern causes formation of sidewalls even at unnecessary portions, that in turn causes to form patterns even at unnecessary portions.